future in vlsi

hi all
Backend VLSI Training Program

Connectlogic is commencing new batch for VLSI training. This training would provide freshers a launching pad to get into VLSI industry.

The training would be aimed towards providing not only extensive theoretical knowledge on the subject but also comprehensive practical skills. Special training & experience on industry standard tool gives add-on advantage to freshers to get through their dream VLSI companies.

Connectlogic possesses highly experienced faculty from VLSI industry. Our faculty members have served in esteemed VLSI companies like ST microelectronics, LSI logic, Jointschip Technologies, Virage Logic, Cypress Semiconductors, ARM Semiconductors, Neomagic Semiconductors, AMI Semiconductors and Freescale Semiconductors.

We have been providing training on VLSI since two years. Connectlogic is also going to start trainings in other domains like Embedded Systems, Digital Signal Processing Processing (DSP) and Telecommunication, within two months. The details of these new courses very soon.
Training Program In Our Organization:
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We Divide the full Chip Development Flow In Backend and Front-end Flow
Backend Flow :Chip Design Cycle

Full Custom Design :
Full custom design includes Memory design, Library Design and all analog design
Training Module in Full Custom
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· Deliberations On functionality according to the requirements and specifications (Developing The specs)
· Developing Mathematical model of circuits.
· Schematic Design with calculated W/L ratios.
· Functional Verification - Include Extensive training on Spice3 standard simulators.
1. Understanding the spice-Berkley models
2. Handling post processing data using perl/shell scripts
3. Understanding the drive strengths / Load design strategies.
4. Understanding the dependencies of W/L ratio on Frequency, input slope, Output load, Vt on Leakage current, Drive Strength, Voltage Regulation

· Translating The Circuit to Layout
Layout Design and Verification Of Layout
Understanding The DRC (Design Rule Checks)
Understanding The LVS (Layout Vs Schematic)
Discussion On Issues like
1. Electro Migration and Solutions
2. Antenna Checks and Solutions
3. Body Effect in Devices and solutions
4. Latch up and Solutions
Extensive Training on Writing DRC rule decks and LVS rule decks for all foundries like TSMC, UMC, STmicro, and Philips.

· Extraction of The design and Final Functional Verification
The Objective Of Backend Training will be to give a full capability to Develop a full custom Library and Memories in Latest Technologies like 0.19u, 0.13u, 90n, and 65n.
Extensive Training will be imparted for CAD specific Expertise.
Special Designed modules to develop capability of creating liberty files .libs for cells of every Complexity.
There Will be a full module on IBIS models (Generation and Use)
Understanding
1. LEF,
2. DEF,
3. EDIF and Their Use
Special training Program to impart training in Perl /Shell scripting Languages.
Further Imparting Training for Specialization in EDA / Front-End / Backend /Embedded as per choice Of candidate.


DIGITAL BACKEND –
There will be a complete and exhaustive module on Place and Route to create full SOC design and all timing related issues will be included in place and route.It will include automatic and timing driven floorplan , placement , routing , Backannotation etc.
On Front End side

Comprehensive training On Digital Design.
Development Of Digital Specs.
Converting The specs into the code (Verilog /Vital)
Putting Constraints on the design during Synthesis.

Comprehensive training to Understand Timing reports
Understanding Timing Violations
Learning to fix these violations.
Development of better design Strategies.
Design Optimization.
Backannotation.
Cloak tree generation and Various strategies.
There will be discussion on Signal Integrity, Place and Route and Test Chip Development.

Extensive training On Full Product Cycle Development.
Understanding Fab Processes for Latest Technologies.



Memory Specific Training
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· Development of Memory Basics.
· Introduction to various memory Architectures.
· ASAP issues.
· Bit cell development (Full Flow)

- Bit Cell Characterization for Leakage current
- Bit Cell Characterization for Write/Read Margins
- Decision On No of physical rows/columns
- Concept Of Column Mux

· Designing Decoder ( x –y )
· Sense Amps and Control Logic
· Memory IO’s
· Development Of Cluster and Instance Generation
· Writing Code for Tiler Engine
· Determination Of Noise .IV Delay, Average Power Dissipation
· Read and Write Cycle timings
· Optimization Of Data Path.

Designing Of IO’s to Synchronize the memory array with Certain drive strengths.
Development Of registerFile with Multiport Read /Write Cycles.
Development Of registerfile via front end Cycle using D-Flops.

Circuit Design and Analog Design Specific Training
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Discussion On Physics Of Semiconductors.
Discussion On Physics Of
- Mos Diodes
- Mos Transistors
- Issues and Effects.

- Latch Up
- Body Effect
- Concept of Threshold Voltage
- Leakage Dependency On Vt
- Differential Vt System
- Deby Length Capacitance
- Miller Capacitance
- Mobility Variation
- Fowler Nordhiem Tunneling
- Drain Punch Through
- Bulk Punch Through
- Drain Induced Barrier Lowering
- Work Function Difference
- Interface Charges
- Vt Adjustment By Ion Implantation
- Concept Of Scaling
- Concept Of scaling regarding Ckt Design
- Technology Migration Regarding Ckt Design
- Short Channel and narrow width Issues
- Gate Induced Drain Leakage
- Poly Gate Depletion Effect
- Early’s Effect

- Introduction To Analog Mosfet Models
- Feedback Concepts
- Amplifier Basics
- Stability Issues.
- Designing Of Mos Amplifiers
- Designing Of Biasing Circuits (Current Mirrors)
- Concepts Of Band Gap
- Designing Of Ios / Buffers
- Designing ADC s/DAC s


Specialized Training Modules
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Library and Technical data control - Cad specific Training
Design and architecture of CAD tools.
Working algorithms of CAD tools.
Programmability Of CAD tools.
Design Automation
Methodologies and Flow
Training In Shell/Perl
Introduction to Linux.
- Concepts Of CVS
- Model generation for Digital libraries.
- Verilog / Vhdl / Vital Modeling of digital libraries.
- Timing Library generation (.lib / .db for cells)


Other Miscellaneous Training includes FPGA and Other Programmable Devices.

Programmable Logic Devices viz. FPGAs, CPLDs and their design tools have changed rapidly in the last 10 years. Today with the advent of Million Gate, High-Performance, System Level Devices, the concept of SOC (System On Chip) is pervading the market of design Field. Now you can create unique designs that were never possible before, get them to market sooner and keep them in the market longer. As a designer, your ‘Design Creativity’ is practically unlimited.
The FPGA and CPLD market is increasing and is about to grow more than the ASIC market, both in terms of devices and value.
Companies like Xilinx, Altera, Quick Logic Cypress are the main Companies in this market.
Million gate devices from them are already available. PLDs are now finding applications in areas, which formerly were the domain of ASICs only.
They are used to describe hardware for the purpose of Modeling, Designing, Simulation, Synthesis, Verification and Documentation.
Support for VLSI design comes from companies like Mentor Graphics, Synplicity, Synopsys, Exemplar, Aldec, Xilinx. They have become the backbone of VLSI Design industry. All these tool support both, VHDL and VERILOG.Thus to support a rapid design FPGA boards are available in market to get the design done in few hours.

[makmayank1987]

what will be the course fee for vlsi training and where will it be held?